Discussion
I'm doing some cursed shit after some ppl in my lab were talking about using chatGPT to lay out a PCB, so since I still have the ridiculously huge token budget from Muse I set it upon the task of "Vibe PCB design" by giving it a link to our paper and telling it to make a replacement for one of the boards in it without looking.
Anyway, look upon splendor, despair, etc.:
https://jon-e.net/lvds-receiver-official/passes/pass-0148.html
I can't waste my EE colleagues time by asking them to eval whether the entire premise of the board would work even if it was laid out perfectly, but I can ask them to look at what they call "pure RF gore." I don't know anything about this, but the AI companies have promised me that's not a problem, that a total noob like me should be able to design their own chip with no expertise, no problem.
@jonny I dunno. Looks good to me. Ship it. We'll just send out a firmware update. I'm sure it'll be fine.
I do think there could be some amazing optimization solvers/auto-routers made for pcb layout that include physics modeling, SI/PI, but GenAI is not that.
You're not going to get there with statistics in part because a lot of people don't understand the nuances and/or rely on old black magic numbers and rules of thumb. Good stuff is protected IP too ...
@fullywoolly one of the goals of this project has become to demonstrate what it looks like for the massive brute force results to play out on a scale that is more familiar to people, where "$20 million dollars of tokens for a math proof" is just an incalculably large sum, but it is visible to see a brute force victory by seeing a timelapse of first extremely busted ass layout and then oh god the hardware simulations to see if it even works on paper...
like yes, intuition and skill is way more efficient way to do it and you'll end up with something better, faster, if you are a mere mortal, but with enough brute force you might get there eventually it's just a monstrously shitty process
The timelapse is already so awesome. Behold, personal superintelligence
so there's a problem... this is a board that is an optical receiver that translates a binary optical signal to digital via a photodiode. You can see that as D1 in the first pic. However the design also specifies that there is a shield can over that area to shield the analog components. This shield also covers the photodiode so... um... well....
The LLM has also designed an entire second fallback build on the same board and left it not hooked up to anything, that's D2 down below, a totally different photodiode that runs at a 400V bias. that's there "just in case"
@jonny reminds me of https://commons.wikimedia.org/wiki/File:CaffeinatedSpider.jpg#/media/File:CaffeinatedSpider.jpg also the "schematic" is pretty great, with all of the passive components having indistinguishable custom rectangular symbols
![EE: I'm checking it, there is so much wrong here that I don't even know where to begin
Me: i bet you guys are always doing this
[a board absolutely littered with via holes, and blue lines just jaggedly scraping their way around them sometimes connected, sometimes not]](https://media.neuromatch.social/media_attachments/files/117/570/792/061/129/326/original/4c6de7877105c8f4.jpg)
![me: that seems good
[the footprint of one IC is riddled with via holes and all the pads are shorted together]
EE: What happened here
[the inside of an IC has a bunch of its pads shorted together by running wires inside the footprint]
me: dog what can I tell you aside from I don't know](https://media.neuromatch.social/media_attachments/files/117/570/792/092/365/926/original/c585955f9762a6a4.jpg)
![[picture of the board with all its components on it, they are all just smashed around in random places and most of them are on top of each other]
me: look at that motherfucker hanging off the side hahahahahahhahaa
EE: Not just that
Almost every component is on top of each other
And for no good reason
There is so much space for routing
me: oh so that's why there are 500 clearance violations every time huh
EE: Very likely kicad just stopped counting at some point](https://media.neuromatch.social/media_attachments/files/117/570/792/122/640/389/original/3a30c2664e3e52a6.jpg)
![Me: I have so many questions but muse keeps telling me its fine
EE: there is so much going on here
[I don't really know how to describe, there's an LED I think? but it has another IC and a bunch of resistors and capacitors inside of it]
Me: I think its actually fine if everything touches
EE: Like sure, things are connected, just in the worst way possible
Me: if things sort of need to be stuffed into the same place then that might cause a little nuclear fusion but otherwise the fab shouldn't have a problem with it](https://media.neuromatch.social/media_attachments/files/117/570/792/181/598/841/original/4c0609b5264768b7.jpg)
It used up all my budgeted 500m tokens for this, but the internal token counts that it has put it at close to 1b tokens - this is a sort of known token accounting mismatch where across all internal surfaces tokens are counted at 2x the rate of client visible counts, and the internal counts are the only ones that actually make sense when estimating from the transcripts.
https://jon-e.net/lvds-receiver-official/tokens/
Token usage · PDLVDS-RX — photodiode LVDS receiver